1. Field of the Invention
This application relates to processor state information and more particularly to reading processor state information non-destructively from a sideband interface.
2. Description of the Related Art
Microprocessors have numerous storage elements that define the processor state. The state of the processor may include, e.g., general purpose registers, fixed and floating point registers, model specific registers, cache related registers, power control registers, test registers, machine-check registers, interrupt registers, timers, and status registers. The specifics of what defines the processor state depends on the particular processor. A processor state can be saved, e.g., prior to entering a power savings mode, and restored by reloading the processor state information. During operation, an unintended change to processor state can result in unpredictable behavior.
During debug, it is often desirable to obtain certain processor state information. That information can be provided over a debug interface, but that type of access typically requires that the processor be stopped in order to access internal processor information. That information in certain circumstances can be obtained without affecting processor state, e.g., by certain types of scan access. When utilizing traditional debug interfaces such as the AMD® hardware debug tool (HDT) debug interface and operating the processor in debug mode, processor type could be obtained on the debug interface. However, in that case reading processor type still requires that the processor be operating in debug mode, which is not feasible in a run-time environment.
During runtime in prior art approaches, processor state information may be obtainable without causing the processor to halt execution; however, obtaining such information may destroy processor state. For example, executing the CPUID command, which obtains a wide variety of processor feature capabilities and configuration information, causes a change to processor state. For example, referring to FIG. 1, software or a debug interface sets the EAX register to the CPUID index. The CPUID index controls the specific information that is returned by execution of the CPUID command. The CPUID instruction is then executed, which takes the EAX register contents (the CPUID index) and utilizes that information to obtain the CPUID information requested. As a result of execution of the CPUID instruction, the EAX, EBX, ECX, and EDX registers are loaded with the specific processor state information requested. That information can then be read by software or from an external debug interface. If this instruction were executed during runtime, i.e., when the processor is executing normally in a system, the change to EAX, EBX, ECX, and EDX registers could cause system instability in currently running software.